The present invention relates to a semiconductor device for controlling electric power and a control method thereof, and more particularly to a semiconductor device capable of improving stability by optimizing the capacitance of a control terminal and a control method thereof.
Generally, IGBT (Insulated Gate Bipolar Transistor) and IEGT (Injection Enhanced Gate Bipolar Transistor) and the like, which control large power using a control terminal having an MOS structure (hereinafter referred to as a gate), are widely used as semiconductor devices for controlling power.
FIG. 1 is a cross-sectional view of a configuration of this type of IGBT. As FIG. 1 shows, a collector electrode 2 is formed on a p-type emitter layer 1, and an n-type base layer 3 is formed on the surface of side which is opposite to the collector electrode 2. P-type base layers 4 are formed on the surface of the n-type base layer 3 by selective diffusion. N-type source layers 5 are selectively formed in the surfaces of the p-type base layers 4.
A gate electrode 7 is formed, via a gate insulating film 6, above the region which extends from one of the n-type source layers 5, through one p-type base layer 4, the n-type base layer 3 and the other p-type base layer 4, to the other n-type source layer 5. Further, a joint emitter electrode 8 is formed on the p-type base layers 4 and the n-type source layers 5.
In order to turn the IGBT ON, with a voltage (main voltage) which is positive with respect to the emitter electrode 8 side being applied at the collector electrode 2 side, a voltage, which is positive with respect to the emitter electrode 8, is applied to the gate electrode 7. As a result, n-type channels are formed on the surfaces of the p-type base layers 4, which are sandwiched between the n-type base layer 3 and the n-type source layers 5, and a current of electrons flows through the n-type base layer 3. And, positive hole current flows from the p-type emitter layer 1 to the n-type base layer 3, causing a conductivity modulation in the n-type base layer 3, whereby the IGBT turns ON.
In order to turn the IGBT OFF, a voltage, which is zero or negative with respect to the emitter electrode 8, is applied to the gate electrode 7. The n-type channels are thereby destroyed, ending the injection of electrons to the n-type base layer 3. As a result, the IGBT turns OFF. In this state, the main voltage is still being applied at the collector electrode 2 side.
When actually manufactured, a plurality of the above type of individually micromachined IGBTs are integrated within a chip. In other words, among the entire plurality of IGBTs integrated in the chip, the IGBT shown in FIG. 1 constitutes a unit region known as a cell, which consists of two IGBTs corresponding to two ends of one gate electrode 7. The IGBTs of these cells are integrated in parallel so as to form a chip-shaped IGBT arrangement.
However, in semiconductor devices such as the IGBT described above, there is the danger that the semiconductor device may become unable to control current as a result of instability of the gate voltage VG or nonuniformity of the ON current (collector current) in the chip or in the cell. This can lead to breakdown of the IGBT itself.
Instability of the gate voltage VG is caused by problems such as noise mixing into the gate circuit, discrepancies in the characteristics of the gate resistors and nonuniformity among the IBGTs.
For instance, FIG. 2 shows a pair of IGBTs 1 and 2 in the ON state, wherein, when 1V of noise becomes mixed into the 300 W gate resistance of the IGBT 1 for a single moment (approximately 10 nsec), the gate voltage VG inclines toward the other IGBT 2 as shown in FIG. 3. Consequently, as FIG. 4 shows, the ON current flows only to the IGBT 2.
The above is only one example of undesired phenomena resulting from noise and the like. Other potential phenomena are oscillation of the gate voltage VG and concentration of current within the cell and the like. When the IGBT is operating at high voltage and high current, any of these phenomena is liable to cause breakdown of the IGBT, lowering the reliability of the semiconductor device.
Furthermore, a system of short-circuit protection is conventionally known as a method for improving the reliability of this type of semiconductor device. FIG. 5 shows a circuit diagram illustrating this short-circuit protection system, and FIG. 6, a front view of the outside of this semiconductor device.
The main element of the semiconductor device is a main IGBT element M1, which is electrically connected in parallel to a sensing IGBT element S1 for detecting current, these elements being provided within a single chip. The area ratio of the elements within the chip may be expressed as in the range of 1:100-1000, the sensing IGBT element S1 being 1, and the main IGBT element M1 being 100-1000.
The current flowing to the main IGBT element M1 is detected from the voltage drop across a resistance Rs which is connected to the emitter of the sensing IGBT element S1. In other words, when large current resulting from a short circuit or the like flows into the sensing IGBT element S1, there is a voltage drop at the resistance Rs. As FIG. 5 shows, this voltage drop causes current to flow to the base of a transistor Tr1, the collector of which is connected to the gate circuit. Consequently, the transistor Tr1 turns ON, reducing the gate voltages of the main IGBT element M1 and the sensing IGBT element S1.
However, the above short-circuit protection has the following disadvantages.
When the operating mode changes abruptly, as when the device is turned ON and OFF, the detected current may not always correspond exactly to the current of the whole IGBT chip. As a result, there are many cases where the protection system fails to operate when a short circuit occurs. An additional disadvantage is that manufacturing discrepancies are considerable.
Moreover, since the sensing IGBT element S1 is provided in the same chip as the main IGBT element M1, there is the disadvantage that the effective area of the main IGBT element M1 is decreased. And, the protection operation tends to be delayed and to suffer from unstable oscillations and the like because the feedback loop from the detection of large current to the gate voltage reduction is so long. Further, once the sensing IGBT element S1 has been provided, it is extremely difficult to perform adjustments and the like to the protection level. There is also the disadvantage that the semiconductor device has a four-terminal structure, comprising the collector, gate and emitter terminals of the main IGBT element M1 and the emitter of the sensing IGBT element S1. The configuration of the semiconductor device is therefore complex and costs are increased.
Next, the protection of the semiconductor device when turned OFF will be described.
A timechart (a) in FIG. 7 is showing the change over time of the voltage VCE, which is applied to the main IGBT element M1, and the current ICE, which flows through the main IGBT element M1, when the main IGBT element M1 is turned OFF. A timechart (b) in FIG. 7 is showing differential versions of the voltage waveforms of (a) in FIG. 7. In each diagram, a solid line is used to depict the state when gate resistance Rg, which is connected is parallel to the MOS gate circuit, is small, and a broken line depicts the state when the gate resistance Rg is large.
When driven by high-frequency signals, the ON/OFF loss (the product of voltage and current integrated over time) not only at the main IGBT element M1 but also in the power element must be reduced. Therefore, the gate resistance Rg must be reduced in order to increase the turn-OFF speed. However, as (b) in FIG. 7 shows, the dV/dt peak value is higher when the time taken to perform turn-OFF is shorter. Here, since the target voltage VCE is fixed, the two differential waveforms shown at (b) in FIG. 7 have equal time axes and areas.
Moreover, in the case where the gate resistance Rg has been reduced to increase the boost rate dV/dt of the voltage VG applied to the main IGBT element M1, when the dV/dt peak value exceeds a predetermined value, there is the problem that the main IGBT element M1 fails to turn OFF and breakdown as a result of displaced current which is proportional to the dV/dt.
On the other hand, in the case where the gate resistance Rg has been increased to protect the main IGBT element M1 from breakdown caused by the dV/dt, there are the disadvantages that turn-OFF speed is slower, there is increased turn-OFF loss, and it is difficult to increase switching speed.
It is therefore an object of the present invention to provide a semiconductor device which is capable of stabilizing gate voltage when operating at high voltage and large current, preventing nonuniformity and oscillation and the like, and improving reliability by protecting the device from breakdown, and a control method therefore.
Furthermore, it is another object of the present invention to provide a semiconductor device which can be protected from breakdown caused by displaced current, thereby improving reliability, by detecting dV/dt at turn-OFF and controlling Rg accordingly.
The present invention has been achieved based on the knowledge, discovered by the present applicant and the like, that one of the main causes of IGBT breakdown is the fact that, at high collector voltage, a gate has negative differential capacitance (CG=dQG/dVG, where QG is charge accumulating at the gate). In other words, the essential point of the present invention is to protect the semiconductor device from breakdown by eliminating negative differential capacitance at the gate, thereby improving the stability of the device.
Next, the knowledge upon which the invention is based will be explained.
As FIG. 8 shows, the present applicant and the like performed tests to determine the gate voltage VG dependency (inclination of which denotes gate capacitance) of the gate charge Qc, for various collector voltages VCE in an IGBT having a dielectric withstanding voltage of 1200V (Toshiba, Product Name: GT25Q101, wherein length of n-type base layer 3 is not less than approximately 100 xcexcm, and density of impurities is not more than: 5xc3x971013 cmxe2x88x923). The gate voltage VG comprises a one-pulse sine wave with amplitude of approximately 15V which is multiplexed onto a direct current bias shown on the horizontal axis. In other words, a conventionally known C-V measuring method could not be used here, because such a method does not take into account the boost in element temperature during measuring. Instead, a one-pulse sine wave was applied to the gate, and the amount of charge flowing into the gate during the application of the sine wave was simultaneously measured. Then, the respective amounts were input to an oscilloscope, with the gate voltage as the horizontal deflection and the charge amount as the vertical deflection. FIG. 8 shows the results obtained. Here, the sine wave frequency is 10-20 kHz.
As FIG. 8 shows, when the collector voltage VCE is 881V, the gate charge QG decreases as the gate voltage VG is boosted, resulting in negative differential capacitance at the gate.
FIG. 9 and FIG. 10 show similar results obtained by simulating the FIG. 8 test. In other words, as FIG. 10 shows, the gate capacitances determined from a simulation reveal that at high collector voltage VCE, negative capacitance occurs above the gate threshold voltage Vth.
This negative capacitance occurs through the mechanism described in (M1)-(M3) below, and results in the effects described in (M4).
(M1) At high collector voltage, positive holes injected from a p-type emitter layer 1 are accelerated by the high electromagnetic field in an n-type base layer 3 and arrive at the interface between the n-type base layer 3 and a gate insulating film 6. (M2) At high collector voltage, the potential of the n-type base layer 3 is higher than the gate voltage VG. As a result, a positive hole channel (accumulation layer) is formed at the interface with the n-type base layer 3. (M3) The positive charge of this positive hole channel causes negative charge within the gate electrode 7, resulting in negative capacitance.
(M4) When a gate resistance is connected to the gate electrode 7, the negative C.R time constant causes instability in the gate voltage VG. Consequently, as FIG. 3 showed, the gate voltage VG either boosts or drops. Moreover, the gate voltage VG is caused to oscillate, which can make the gate impossible to control.
This type of negative capacitance can be expressed by an equation to be explained below.
FIG. 11 shows the above mechanisms (M1)-(M3) in more detail. The circuit shown in FIG. 11 can be substituted by the equivalent circuit of FIG. 12. The equivalent circuit shown in FIG. 13 illustrates the relation between capacitance and voltage at each component.
Based on the equivalent circuit of FIG. 12, the electronic current Ie, which is injected via the n-channel at the interface with the p-type base layer 4 to the n-type base layer 3, can be expressed by the following equation (1):
Ie=gmn-ch(VGExe2x88x92Vthn-ch)xe2x80x83xe2x80x83(1)
Here, gmn-ch denotes the mutual conductance, and VGxe2x88x92Vthn-ch denotes the threshold voltage of the n-channel.
And, hole current Ih, which is injected from the p-type emitter layer 1,can be expressed by the following equation (2) using the current amplitude rate xcex2 of the pnp transistor portion of the IGBT (IEGT)
Ih=xcex2Iexe2x80x83xe2x80x83(2)
Assuming a case in which the hole current Ih passes through all the p-channels on the interface with the n-type base layer 3 as it flows to the p-type base layer 4, the hole current Ih can be expressed with the following equation (3):
Ih=gmp-ch(Vpchxe2x88x92VGxe2x88x92Vthp-ch)xe2x80x83xe2x80x83(3)
Here, an equation expressing the relations of voltages of all components can be obtained by substituting equation (1) and equation (2) into equation (3) as follows:
gmp-ch(Vpchxe2x88x92VGxe2x88x92Vthp-ch)=xcex2gmn-ch(VGxe2x88x92Vthn-ch)xe2x80x83xe2x80x83(4)
And, from the equivalent circuit shown in FIG. 13, charge xcex94QG which is accumulated at the gate can be expressed as follows:
xcex94QG=CG-Sxcex94VGE+CG-p-chxcex94(VGExe2x88x92Vpch)
Equation (4) gives: xcex94(VGExe2x88x92Vpch)=xe2x88x92xcex2 (gmn-ch/gmp-ch)xcex94VGE. Therefore, the gate capacitance CG can be expressed with the following equation (5):
CG=xcex94QG/xcex94VGE=CG-Sxe2x88x92CG-p-chxc2x7xcex2xc2x7gmn-ch/gmp-chxe2x80x83xe2x80x83(5)
The second article on the right side of the above equation has a negative value, which causes negative capacitance.
The knowledge relating to negative (differential) capacitance explained above has been discovered for the first time through research conducted by the present applicants and the like.
Next, the essence of the present invention, which is based upon this knowledge, will be explained.
FIG. 14 and FIG. 15 show the negative capacitance of FIG. 10 in schematic form. The gate capacitance CG is considered to be a parallel compound capacitance including a capacitance C2, comprising n-type base layer 3/gate insulating film 6 gate electrode 7, and a capacitance C1, comprising (n-type source layer 5xc2x7p-type base layer 4)/gate insulating film 6/gate electrode 7.
As FIG. 16 shows, the capacitance C1 has an almost constant value which is unrelated to the gate voltage VG. As FIG. 17 shows, the capacitance C2 decreases in a step shape as the gate voltage VG rises. As can be supposed from FIG. 10, the ratio between positive capacitance C2+ and negative capacitance C2xe2x88x92 is approximately 2:1.
As FIG. 18 shows, the present invention eliminates negative capacitance C2xe2x88x92 by actively increasing capacitance C1, thereby raising the bottom of the capacitance C2. More specifically, C1 greater than C2xe2x88x92=(xc2xd) C2+. In other words, when the following equation (6) is satisfied, gate capacitance CG always has a zero or positive value, never a negative value.                               C1                                    C2              +                        +            C1                          ≧                  1          3                                    (        6        )            
Equation (6) can easily be realized by, for instance, designing a mask pattern using an area (corresponding to C2) having a MOS configuration, including an n-type base layer 3, and an area (corresponding to C1) having a MOS configuration, including an n-type source layer 5 and a p-type base layer 4. Furthermore, equation (6) can be realized not only in the areas having MOS configurations, but also, for instance, by setting the thickness and material (permittivity xcex5) of the gate insulating film used in the MOS configurations to correspond to the capacitances C1 and C2. Moreover, another phrase instead of xe2x80x9carea having a MOS configurationxe2x80x9d can be substituted in equation (6), provided that the substitution is equivalent. Or, xe2x80x9carea of capacitance C2/total gate area=not more than ⅔xe2x80x9d can be replaced by a different relationship.
The above knowledge, as well as the relation of the length of the n-type base layer 3 to the design parameters of the elements, have been confirmed by the method explained below. The length of the n-type base layer 3 (hereinafter N base length) referred to here corresponds to the distance covered by the n-type base layer 3 from the p-type emitter layer 1 to the bottom of the p-type base layer 4, the n-type base layer 3 being provided therebetween.
FIG. 19 is a graph illustrating a relationship between the length of the n-type base layer 3 and C1/(C2++C1) which was confirmed using four IGBTs. As FIG. 19 shows, when the length of the n-type base layer 3 is 100 xcexcm, the C1/(C2++C1) value dropped from 0.33 to 0.2 (from ⅓ to ⅕). Thus it can be seen that the problem arises directly from the conventional notion that the gate length LG should be increased as the N base length increases due to the need to increase the number of carriers accumulating in the n-type base layer 3. In other words, the problem lies in the conventional method of design, wherein the length of the gate length LG is increased in order to stimulate the injection of electrons from the MOS channel, producing a low ON voltage. To achieve this, the C2+ value is increased and the C1/(C2++C1) is lowered. But as a result, the C2xe2x88x92 value also increases, facilitating the generation of negative gate capacitance
Therefore, gate instability was investigated, using a noise pulse in the manner already described, for the two states shown in FIG. 19, namely an IGBT in which C1/(C2++C1)=0.33 (the IGBT elements having N base length of approximately 63 xcexcm, hereinafter referred to as IGBT elements A) and an IGBT in which C1/(C2++C1)=0.2 (the IGBT elements having N base length of approximately 100 xcexchereinafter referred to as IGBT elements B).
As FIG. 20 shows in detail, the two IGBT elements A1 and A2 are connected in parallel. Noise was applied into the gate of IGBT element A2 and the behaviour of the gate voltage was observed. The same test was performed using IGBT elements B1 and B2.
The results showed that when IGBT elements A1 and A2 were connected in parallel, the noise pulse caused a brief fluctuation in the gate voltages, but the gate voltages soon stabilized on the gate bias voltage (a voltage applied by means of a gate signal).
In contrast, as FIG. 21 shows, in the case of IGBT elements B1 and B2, the oscillations of the gate voltages following the application of noise did not stabilize and, actually increased. Moreover, since the noise pulse was applied to IGBT element B2, the gate voltage VG of the other IGBT element B1 oscillated widely. As a result, negative capacitance caused instability leading to oscillation between the IGBT elements B1 and B2, which are provided in parallel.
The above results show that when (C1/C2++C1) greater than 0.33, there is not instability, but when (C1/C2++C1) greater than 0.2, instability, such as oscillation and current nonuniformity, occurred. In view of such instability, the value of (C1/C2++C1) must be greater than at least 0.2 (=⅕) and, more preferably, greater than 0.33 (=⅓).
Furthermore, when the N base length exceeds 100 xcexcm, the value of (C1/C2++C1) falls to below approximately 0.2, as in the conventional design method. Therefore, the present invention is particularly effective for elements with an N base length exceeding 100 xcexcm.
When the N base length exceeds 300 xcexcm, the value of (C1/C2++C1) falls even further to less than approximately: 0.1 (={fraction (1/10)}). Therefore, in the case of elements having N base length exceeding 100 xcexcm, the value must be raised to at least 0.2 (=⅕) in order to effectively correct the nonuniformity.
The above explanation referred to planar-type elements, but the research conducted by the present applicant has confirmed that similar negative capacitance occurs in the case of trench-type elements. However, the ratio of C2+:C2xe2x88x92 was found to be slightly different in the case of trench-type elements.
FIG. 22 is a diagram showing a configuration of a trench-type IEGT element without a gate bypass, FIG. 23, a diagram showing a configuration of a trench-type IEGT element with a gate bypass, and FIG. 24, a diagram showing the gate voltage dependency of a gate capacity in these two types of IEGT elements. In the present application, xe2x80x9cbypassxe2x80x9d denotes the omission of the n-type source layers 5.
In other words, instead of planar-type gate insulating films 6 and gate electrode 7 depicted in FIG. 22, the IEGT element TA, which does not have a bypass, comprises trenches dug in the surface of the n-type source layers 5 and extending through the p-type base layers 4 to a depth in the n-type base layer 3. Gate electrodes 7, which are provided on the p-type base layers 4 sandwiched between the n-type base layer 3 and the n-type source layers 5, are buried within the trenches and surrounded by gate insulating film 6 therein. These gate electrodes 7 are connected to a gate terminal which is not shown in the diagram.
In contrast, as FIG. 23 shows, the IEGT element TB differs from FIG. 22 in that it comprises p-type base layers 4 having n-type source layers 5, and p-type base layers 4 having no n-type source layers 5, these being arranged between the trenches alternately.
As FIG. 24 shows, the non-bypass IEGT element TA contains a slight portion where the gate capacitance has a negative value. However, the bypass IEGT element TB has a considerable negative gate capacitance CG.
The changes in the gate capacitances CG of such trench-type elements are complicated, but it can be clearly seen that the ratio between C2+:C2xe2x88x92 becomes C2+:C2xe2x88x92=5:1 in the non-bypass configuration, and becomes C2+:C2==4:1 in the bypass configuration.
Consequently, in a non-bypass configuration, the value of C1/(C2++C1) should preferably be no less than ⅙. Similarly, in a bypass configuration, the value of C1/(C2++C1) should preferably be no less than ⅕.
In FIG. 24, the gate voltage has its negative peak close to 4.5V. This negative peak has little influence on breakdown, since the negative peak occurs in an area of low current where the collector current has a small value, and can therefore be ignored.
Next, the method for controlling the semiconductor device based on research conducted by the present applicant will be explained.
As FIG. 25 and (a)-(b) in FIG. 26 show, the above research revealed that when the IGBT suffers a short circuit, the amount of charge accumulated at the gate is less than during normal operation. In other words, the state in which the charge accumulated at the gate has decreased can be viewed as evidence of a short circuit. Furthermore, when a short circuit has been detected in this way, the IGBT can be protected from the short circuit by lowering the gate voltage.
FIG. 27 shows a block diagram of a short-circuit protection circuit, which has been devised based on the above knowledge, wherein a charge counter is connected in series to a gate circuit of a main IGBT element M1.
In addition, a transistor Tr1 is connected between the gate circuit and earth.
A differential amplifier AM1 consults the gate voltage and determines whether or not the gate charge counted by the charge counter is lower than a predetermined value (the prohibited area of FIG. 25). When the differential amplifier AM1 has determined that the amount of charge is less than the predetermined value, the differential amplifier AM1 lowers the gate voltage.
The method for counting the amount of charge at the gate can also be similarly used for counting voltage and current at any given circuit.
Yet another method for controlling a semiconductor device will next be explained relating to dV/dt detecting. Here, the semiconductor device comprises a dV/dt detecting element which is electrically connected in parallel to a main switching element. Gate resistance is controlled in accordance with the detected result of this dV/dt detecting element.
Consequently, the main switching element can be turn OFF more quickly within a non-breakdown range. In addition, the amount of OFF loss can be reduced.
The measures used by the invention to achieve the object, based on the knowledge and essential points explained above, are as follows.
A first aspect of the invention provides a semiconductor device, comprising a base layer of the first conductivity type; an emitter layer of the second conductivity type, formed on a surface of the base layer of the first conductivity type; a collector electrode, formed on a surface of the emitter layer of the second conductivity type; a base layer of the second conductivity type, formed in a surface of the base layer of the first conductivity type which is opposite to the emitter layer of the second conductivity type; a source layer of the first conductivity type, formed in a surface of the base layer of the second conductivity type; an emitter electrode, formed on the source layer of the first conductivity type and the base layer of the second conductivity type; and a gate electrode, contacting the source layer of the first conductivity type, the base layer of the second conductivity type and the base layer of the first conductivity type, with a gate insulating film interposed therebetween; wherein when a voltage is applied between the collector electrode and the emitter electrode, capacitance of the gate electrode is always a positive value or zero.
According to a second aspect of the semiconductor device of the invention, when the flow of current between the collector electrode and the emitter electrode is interrupted, the minimum value of the capacitance is not less than a third of the maximum value of the capacitance.
According to a third aspect, the area of a portion of the gate electrode which contacts the base layer of the first conductivity type, with the gate insulating film therebetween, is not more than two thirds of the whole of the area of the gate electrode.
Moreover, according to a fourth aspect, the length of the base layer of the first conductivity type is not less than 100 xcexcm.
According to a fifth aspect, the semiconductor device of the invention comprises a base layer of the first conductivity type; an emitter layer of the second conductivity type, formed on a surface of the base layer of the first conductivity type; a collector electrode, formed on a surface of the emitter layer of the second conductivity type; a base layer of the second conductivity type, formed in a surface of the base layer of the first conductivity type which is opposite to the emitter layer of the second conductivity type; a source layer of the first conductivity type, formed in a surface of the base layer of the second conductivity type; an emitter electrode, formed on the source layer of the first conductivity type and the base layer of the second conductivity type; a gate electrode, buried inside a first trench with a gate insulating film interposed therebetween, the first trench being provided extending from a surface of the source layer of the first conductivity type, through the base layer of the second conductivity type, to a depth within the base layer of the first conductivity type; and a buried electrode, buried inside a second trench with a gate insulating film interposed therebetween, the second trench being provided extending from a surface of the base layer of the second conductivity type to a depth within the base layer of the first conductivity type; wherein the buried electrode and the emitter electrode are electrically connected and substantially have a same potential.
According to a sixth aspect, the relation between the buried electrode and the emitter electrode is altered, so that the buried electrode has a fixed potential which is lower than the potential of the emitter electrode.
Next, according to a seventh aspect of the invention, a method for controlling a semiconductor device, having two main electrodes and a control electrode which controls a current flowing between the main electrodes, comprises steps of: detecting an amount of charge accumulated at the control electrode based on a voltage of the control electrode; and controlling a voltage applied to the control electrode and/or current flow to the control electrode based on a charge amount detected by the detecting.
Furthermore, according to an eight aspect, when the amount of charge has a negative value, the applied voltage and/or the current flow is/are lowered by the controlling.
Moreover, according to a ninth aspect, a method for controlling a semiconductor device, having two main electrodes and a control electrode which controls a current flowing between the main electrodes, comprises steps of detecting current, which crosses through the control electrode, before and after the current crosses; and
controlling a voltage applied to the control electrode and/or current flow to the control electrode based on a difference between current detected before crossing and current detected after crossing.
Furthermore, according to a tenth aspect, the step of controlling comprises: reducing a voltage applied to the control electrode and/or current flow to the control electrode when an integral of the difference has a negative value.
Moreover, according to an eleventh aspect, the semiconductor device comprises a switching element, comprising a first high voltage side main electrode, a low voltage side main electrode and a gate electrode; an electrode for sensing, comprising a second high voltage side main electrode, which is joined with the first high voltage side main electrode, and an electrode for detecting potential, the electrode for detecting potential formed on a substrate surface on a side of the low voltage side main electrode and electrically connected, via a resistance component, to the low voltage side main electrode; a gate resistance controller for controlling the value of a gate resistance between the gate electrode and a gate driver based on a potential of the electrode for detecting potential; wherein when the switching element is turned OFF, the gate controller detects as voltage boost rate dV/dt, by means of the electrode for detecting potential, and raises the value of the gate resistance, thereby restricting the voltage boost rate dV/dt.
By instituting the means described above, in the first aspect of the invention, when a voltage is applied between the collector electrode and the emitter electrode, the resistance of the gate electrode is always a positive value or zero. By eliminating negative differential capacitance at high collector voltage in this way, the gate voltage can be stabilized and current nonuniformity and oscillation and the like can be prevented, even at high voltage and high current. Consequently, the device can be protected from breakdown and reliability can be improved.
In the second aspect of the invention, when the flow of current between the collector electrode and the emitter electrode is interrupted, the minimum value of the capacitance is not less than a third of the maximum value of the capacitance. Consequently, the effects of the first aspect can be more easily and reliably obtained.
Moreover, in the third aspect of the invention, the area of the portion of the gate electrode which contacts the base layer of the first conductivity type, with the gate insulating film interposed in between, is not more than two thirds of the whole of the area of the gate electrode. Consequently, the effects of the first aspect can be even more easily and reliably obtained.
Furthermore, in the fourth aspect of the invention, since the length of the base layer of the first conductivity type is not less than 100 xcexcm, the effects of the third aspect can be achieved even in a semiconductor device operating at a dielectric withstanding voltage greater than, for instance, approximately 1200V.
In the fifth aspect of the invention, further provided is a buried electrode, which has the same configuration as the gate electrode but is not wired to the gate circuit (namely, an ineffective gate electrode). The buried electrode is fixed at the same potential as the emitter electrode, thereby enabling negative charge generated at the ineffective gate to be discharged, preventing any effects caused by the negative charge.
Further, in the sixth aspect of the invention, the buried electrode has a fixed potential which is lower than the potential of the emitter electrode. Consequently, it is possible to reduce the amount of recombination on the trench insulating film interface of the ineffective gate electrode, increase the accumulated carriers in the first conductive base payer, and thereby reduce the negative gate capacitance.
Moreover, in the seventh and eighth aspects of the invention, the amount of charge at a control electrode is detected, and when the charge amount is found to have a negative value, this is regarded as indicating a short circuit. Then, the applied voltage and/or the current flow to the control electrode is/are lowered, thereby protecting the semiconductor device from the short circuit.
In the ninth and tenth aspects of the invention, current which crosses through the control electrode, is detected before and after crossing, and the voltage applied to the control electrode and/or current flow to the control electrode is/are reduced when the integral of the difference between the currents detected has a negative value, thereby protecting the semiconductor device from the short circuit.
Finally, in the eleventh aspect of the invention, gate resistance is small during normal ON, but at turn OFF, the voltage boost rate dV/dt is detected and the gate resistance is charged to large. Consequently, breakdown due to high dV/dt when the main switching element is turned OFF can be prevented. In addition, turn OFF can be performed more quickly with reduced OFF loss.
Additional objects and advantages of the present invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the present invention.
The objects and advantages of the present invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.